The present disclosure relates to semiconductor structures, and particularly to replacement gate semiconductor structures employing a planarization dielectric layer that is planarized without formation of divots or recesses on a top surface thereof, and methods of manufacturing the same.
The use of silicon oxide as gate spacers and/or a planarization dielectric layer results in formation of recesses and divots on the planarized top surfaces of the silicon oxide material. For example, in a semiconductor structure employing a silicon oxide gate spacer and a silicon oxide planarization dielectric layer, removal of a disposable gate material in a replacement gate processing scheme results in collateral etch of the top portions of the silicon oxide gate spacer and top portions of the silicon oxide planarization dielectric layer relative to a top surface of another planarization dielectric material such as silicon nitride. Divots and/or recesses are formed above the top surfaces of the recessed portions of the oxide material.
During deposition of a conductive material for formation of metallic gate structures, such divots and/or recesses are filled with the conductive material. Such residual conductive material filling divots and/or recesses provide a spurious conductive path, causing electrical shorts between various semiconductor devices. Thus, the residual conductive material is a concern for reliability and yield.